Recently, a multiport video RAM (MPRAM) has drawn attention as a memory suitable for high speed data processing and displaying in the fields of engineering work stations (EWS), computer graphics (CG), and the like. This MPRAM has a random access port (RAM port) having a memory array (e.g., DRAM) randomly accessible and a serial access port (SAM port) having a serial access memory cyclically and serially accessible.
In an MPRAM, data is transferred between the RAM port and SAM port. It is necessary to synchronize data transfer timings only during the transfer cycle. The timings during the transfer cycle will be described with reference to FIGS. 1A and 1B.
Referring to FIG. 1A, there will be described the case wherein data at a certain row R in a memory array 101 of a RAM port is transferred to a serial access memory 102 having a SAM port which continuously executes serial access. In this case, an external signal DT for controlling transfer is first caused to fall (at time T1 in FIG. 1B). If the external signal DT takes an "L" level at the time when a signal RAS falls, then the transfer cycle starts. During this transfer cycle, similar to an ordinary RAM cycle, a row address and column address are supplied synchronously with the trailing edges of RAS and CAS (at times T2 and T3). The row address indicates a row of transfer data in the memory array 101, and different from an ordinary RAM cycle, the column address indicates a TAP address representative of the position of a new serial cycle after the data transfer. The transferred data is outputted starting from the TAP address at the serial cycle (time T6) after the external signal DT rises.
It is necessary for the external signal DT to rise at the timing (time T5) between the rising timing (time T4) and next rising timing (T6) of a serial clock signal SC. Therefore, time periods t1 (=T5-T4) and t2 (T6-T5) have some restriction. Such restriction of the time periods t1 and t2 is very severe for the application to practical products because the cycle time of the serial clock signal SC is 30 to 40 nsec.
In order to mitigate such restriction, a split transfer system has been proposed.
This split transfer system will be described with reference to FIGS. 2A and 2B. A serial access memory 102 having a SAM port to which the split transfer system is applied is divided into two groups of SAM (L) and SAM (U). The divided SAM (L) and SAM (U) correspond to "0" and "1" of the most significant bit (MSB) of the TAP address. It is therefore possible to transfer data from RAM 101 to SAM (L) and SAM (U) independently from each other. It is assumed that SAM (L) is now serially accessed. Consider the case wherein during this serial access a transfer cycle occurs, and the data at a row R of a memory array 101 having a RAM port is transferred to SAM 102. Similar to the case of FIG. 1A, the row address at this time indicates the row R. MSB of the TAP address is set to MSB (in this case "1") on the SAM side which is not now serially accessed. SAM for which transfer operation is carried out is SAM (U) with MSB set. The data transferred to SAM (U) is accessed starting from the TAP address with newly set MSB, when the serial access further continues and changes from SAM (L) to SAM (U). In the case shown in FIG. 2B, during the transfer cycle for the serial address 0 to 127, data in RAM 101 at the row R is transferred to SAM (U) at addresses 128 to 255. As the serial access advances to an address 127 and enters the next SC cycle, the TAP address is accessed to further continue the serial access. As described above, since the divided serial memory unit serially accessed and the divided serial access memory to which data is being transferred are different, there is no timing restriction as described with FIG. 1B.
Such split transfer will be described with reference to a more particular circuit diagram.
FIG. 3 is a schematic diagram illustrating a split data transfer state and a correspondence between RAM 1, SAM 2, and transfer gates interconnecting RAM 1 and SAM 2. FIG. 4 is a circuit diagram showing the details of a portion of FIG. 3.
Referring to FIG. 3, for the split data transfer, RAM 1 is divided into a first lower RAM unit 1 corresponding to MSB=0 of the column address, and a second upper RAM unit b corresponding to MSB=1. As seen from FIG. 4 which will be later described in detail, each column of RAM 1 is in one-to-one correspondence with each column of SAM 2. Accordingly, during the split data transfer, data in a memory cell MC belonging to the lower (MSB=0) first RAM unit a is transferred to a register j of a lower first SAM unit c, whereas data in a memory cell MC belonging to the upper (MSB=1) second RAM unit b is transferred to a register j of an upper second SAM unit d.
FIG. 4 shows the details of the first RAM unit a and first SAM unit c, respectively for MSB=0. In FIG. 4, the circuit portion for four columns is shown. Each column has a pair of bit lines BL and BL. The RAM unit a has a cell array h constituted by a plurality of memory cells MC connected to the bit lines BL and BL, bit line equalizing transistors f for equalizing pairs of the bit lines BL and BL, and RAM unit DQ gates e for data transfer to and from an external circuit.
The SAM unit c is connected via the data transfer gates i to the RAM unit a. The SAM unit c functions as a serial register for the RAM unit a, and has SAM data registers j and SAM unit SDQ gates k.
The RAM unit b and SAM unit d are constructed in the similar manner described above.
If continuous read/write, for example, is to be executed by the split data transfer using the device shown in FIGS. 3 and 4, the two upper and lower RAM units a and b are alternately accessed depending upon whether MSB of the column address is "0" or "1". Therefore, continuous access within the same RAM unit cannot be allowed. Namely, different memory cells within the lower (MSB=0) first RAM unit a cannot be accessed continuously, neither different memory cells within the upper (MSB=1) second RAM unit b can be accessed continuously. A memory which cannot execute such an access is not proper in displaying an image at high speed on a CRT or the like. This is an issue newly recognized solely by the present inventors. The above discussion will be further described in detail from a different viewpoint.
Next, there will be described a method of configuring a data buffer for processing displayed data on a screen at high speed using the split transfer method.
A DRAM is used as a random access memory for MPRAM. If data at the same row is accessed using the page mode for DRAM, data can be accessed in a time period 1/2 to 1/3 time as short as the time period required when data is accessed by changing the row address. The data at one row corresponds to the data to be serially outputted from the SAM unit. This serial data becomes a pixel data on a display screen. How pixel data is disposed on a screen is important for high speed screen processing. In the screen processing, if pixels within a square area can be processed at high speed, any type of pattern processing can be executed at high speed. Namely, screen processing can be executed at high speed in any direction including a vertical direction, horizontal direction, and oblique direction. It becomes therefore important how the data at one row accessible by the page mode is allocated in the vertical direction relative to the scan direction of the display screen.
Consider now the case where a screen is constituted by using sixteen DPRAM's, four in the scan direction and four in the vertical direction, i.e., a 4.times.4 tile structure is adopted. FIGS. 5A and 5B show DPRAM's of the split transfer type wherein data at one row of a random access memory (RAM) has 256 bits, and data of a serial access memory (SAM) also has 256 bits. The screen size is assumed to have 1536 pixels in the scan direction, for the simplicity of description. Referring to FIG. 5A, R0, R1, R2, . . . represent a row of RAM 101, and 0 to 127 (L) and 128 to 255 (U) in the column direction represent a column of RAM 101 from which data is split-transferred to SAM 102 divided into two blocks.
The length in the scan direction of a single tile is 128.times.4=512 bits because four devices M1, M2, M3, and M4 are used and each divided partial SAM has 128 bits. The length in the vertical direction is 2.times.4 devices=8 bits. Therefore, three (1536/512=3) tiles are disposed in the scan direction of the screen. If the partial SAM (L) and partial SAM (U) are assigned to pixels in the vertical direction, screen processing for a shape more like a square can be executed through an access of one row by the page mode. Data in the RAM unit is split-transferred in the order of R0L, R1U, R2L, R0U, R1L, R2U, . . . The SAM unit 102 serially outputs the data to scan pixels. Of the data on the screen, an area indicated by hatched lines in FIG. 5B is made of the R0 data in the four devices. Any desired portion of the area R0, for example, of the four devices can be accessed by the page mode. The screen is filled with tiles as indicated by hatched lines in FIG. 5B, and the tile can be accessed by the page mode. In other words, high speed screen processing becomes possible.
The data structure in the scan direction will be further described in detail. FIG. 6 illustrates in what way pixels are constituted using serial data from four MPRAM's. The four bit output data from SAM's of the devices M1 to M4 is applied to a parallel/serial converter circuit (refer to FIG. 6(a)), and outputted therefrom as one bit serial data so that pixels of the screen are formed one point after another. With such an arrangement, SAM can be serially accessed at the speed 1/4 time as slow as the screen display speed, thereby reducing the load on SAM. The pixel data subjected to such parallel/serial conversion becomes a repetition of data from DPRAM's of M1, M2, M3, and M4 in this order in the scan direction (refer to FIG. 6(b)). The data in each frame of R0L and R0U within the tile shown in FIG. 5B has such a data structure.
The case where the screen size is different from the above-described size will then be described.
FIGS. 7A and 7B illustrate the case where the number of pixels in the scan direction is 1024. The tile size is assumed to be constituted by using 4.times.4 MPRAM's similar to the above-described case. In this case, two (1024/512=2) tiles are disposed in the scan direction of the screen. In order to make divided data U and L at one row correspond to the pixel disposal in the vertical direction of the screen, it is necessary to split-transfer the data in the order shown in FIG. 7A. Specifically, if the data is transferred in the order of R0L, R1U, R0U, R1L, . . . , then the area indicated by hatched lines in FIG. 7B can be freely accessed by the RAM page mode. In this data transfer, however, L and U are crossed relative to SAM so that a conventional split transfer cannot deal with it. If a split cross transfer is adopted which can transfer data from U of SAM to L of SAM, or from L of RAM to U of SAM, then the data transfer shown in FIG. 7A becomes possible while allowing to deal with the case wherein an even number of tiles are disposed in the scan direction of the screen. This is an issue newly recognized solely by the present inventors.
As discussed previously, it is more suitable for high speed screen processing if data in RAM in the column direction accessible at high speed is made to correspond to a pixel area on the screen having a shape more like a square. However, so long as SAM is used as two divided units as in the above-described cases, the length of a tile in the scan direction becomes longer than that in the vertical direction, which is a disadvantage in high speed screen processing. Such disadvantage can be dealt with by changing the size of a tile. However, a change of a tile size results in that a buffer memory system design is required to be changed depending on the size of a screen.
Such a problem will be described further from a different viewpoint.
In a graphics system frame buffer using multiport video RAM's having a split transfer function, the SAM port is used for outputting and displaying data on a CRT, and the RAM port is used for inputting/outputting image data relative to a graphics processor. This buffer operates to store image data and output data to a CRT at high speed. For outputting data to a CRT, it is necessary to output the data continuously and at high speed. To this end, as described above, a split transfer function is provided so that data output from SAM and data transferred from RAM to SAM are alternately interleaved while dividing the SAM register and RAM cell array into two blocks, respectively.
A frame buffer using multiport video RAM's of a conventional split transfer type will be described. Each dot on a CRT screen in the vertical direction is made in correspondence with each cell data aligned in row direction. In such a case, if a CRT is mapped as shown in FIG. 8, then the corresponding cells in multiport video RAM's are disposed as shown in FIG. 10. The scan lines on the CRT are traced in the order of 1, 2, 3, 4, . . . shown in FIG. 8. Therefore, SAM's of the multiport DRAM's correspondingly output the data in the RAM cell array in the order of 1, 2, 3, 4, . . . In this case, it is necessary that SAM's output data be continuous data. To this end, a split transfer is used to output data alternately from SAM registers a and b such that while one SAM register outputs data, the other SAM register receives new data transferred from the RAM array. In a multiport video RAM without a cross transfer function, it is decided that the left half RAM cell array of FIG. 10 can be connected to the SAM register a and the right hand RAM cell array can be connected to the SAM register b. Therefore, the mapping shown in FIG. 8 essentially leads to the mapping shown in FIG. 10. 1 and 2, 3 and 4, . . . shown in FIG. 10 represent cells on the same row. It is therefore possible to write data of the RAM port at high speed, and as viewed from the CRT screen it is possible to write a horizontal line at high speed. However, it is necessary to write data into cells at different rows, in order to display a vertical line on the CRT screen. As a result, on the side of the RAM port, normal write cycles are required to be used for all data write, taking a very long time. The image data write speed from a graphics processor to a multiport video RAM therefore depends upon a vertical line.